Plasma immersion ion implantation is performed by generating a plasma containing ions of species to be implanted in a semiconductor wafer or workpiece. The plasma may be generated using a plasma source such as a toroidal plasma source at the reactor chamber ceiling. Ion energy sufficient to achieve a desired ion implantation depth profile below the wafer surface is provided by coupling a very high RF bias voltage (e.g., 10 kV to 20 kV) to the semiconductor wafer through an insulated cathode electrode within the wafer support pedestal. If the wafer support pedestal is incorporated within an electrostatic chuck, then the insulated cathode electrode may be a thin metal (e.g., molybdenum) mesh separated from the wafer support surface by a thin (e.g., 1 mm thick) insulation layer. The wafer is electrostatically clamped to the chuck by applying a D.C. clamping or “chucking” voltage to the mesh electrode, to induce a strong electric field across the thin insulation layer under the wafer. A high RF bias voltage (10-20 kV) is required to achieve the desired ion implantation depth profile. The wafer is electrostatically clamped to achieve good temperature control. The RF bias power applied to the wafer to control ion energy or implant depth produces a wafer DC bias voltage. The desired electrostatic wafer clamping voltage is produced by applying a DC voltage to the chuck mesh electrode that differs from the wafer DC bias voltage by an amount equal to the desired clamping voltage. The difference is the wafer clamping DC voltage, which is typically 1-2 kiloVolts for a coloumbic chuck and 400-600 Volts for a Johnson-Rahbeck chuck.
The D.C. clamping voltage produces a correspondingly large amount of electrical charge trapped in the interface between the wafer backside and the thin insulation layer. This trapped charge produces a strong attractive force between the wafer and the chuck even after removal of the D.C. chucking voltage. Any attempt to remove the wafer from the chuck without waiting for the trapped charge to dissipate risks breaking the wafer. The problem is that it may take 1-24 hours for the trapped charge to dissipate sufficiently to remove the wafer. This is because the wafer has an insulating (silicon dioxide) layer on its backside and the wafer support surface is covered by an insulating (e.g., silicon dioxide or silicon nitride) seasoning layer. The leakage or neutralization of the trapped charge through these insulating layers is extremely slow. The resulting delay (1-24 hours) from waiting for the dissipation of the trapped charge represents a costly reduction in throughput. There is a need to overcome this limitation on productivity.